module uart_top(CLK,BAUD_DETECTION,RSTN,SENT,DATA,TXD,RXD);
input CLK,BAUD_DETECTION,RSTN,SENT,RXD;
output TXD;
output[7:0] DATA;
wire CLK,BAUD_DETECTION,RSTN,SENT,RXD,TXD;
wire[7:0] DATA;
wire BAUD16;
control_baud control_baud(.CLK(CLK),.BAUD_DETECTION(BAUD_DETECTION),.RSTN(RSTN),.SAMPLING(BAUD16));
uarttx uarttx(.SENT(SENT),.RSTN(RSTN),.CLK(BAUD16),.TXD(TXD));
uartrx uartrx(.CLK(BAUD16),.RSTN(RSTN),.RXD(RXD),.DOUT(DATA));
endmodule